A 64/spl times/64-bit modified Booth multiplier utilizing multiplexer-select Booth encoder

摘要

In this paper, we describe a 64/spl times/64-bit high performance multiplier based on multiplexer cells which is implemented with pass transistor logic. A multiplexer-select Booth encoders was developed to increase speed and reduce the hardware cost. Moreover, a partitioned method was introduced in the design to save the propagate time of final adder. Realistic simulation using extracted timing parameters from the layout shows that the propagation time of the critical path is 2.82ns at 1.8V on 0.18/spl mu/m CMOS technology.