60 GHz CMOS power amplifier with P_sat of 11.4 dBm and PAE of 15.8%

摘要

A 60 GHz power amplifier (PA) for a direct-conversion transceiver using standard 90 nm CMOS technology is reported. The PA comprises three cascaded common-source stages with inductive load and inter-stage matching. To increase the saturated output power (P_sat) and power-added efficiency (PAE), the output stage adopts a twoway power dividing and combining architecture. Instead of the area consumed Wilkinson power divider and combiner, a miniature lowloss LC power divider and a combiner are used. This in turn results in further P_sat and PAE enhancement. Over the 57??64 GHz band of interest, the PA consumes 44.4 mW and achieves a power gain (S₂₁) of 12.04 + 1 dB. At 60 GHz, the PA achieves P_sat of 11.4 mW and a maximum PAE of 15.8%. To the authors?? knowledge, this is the best PAE ever reported for a 60 GHz CMOS PA. These results demonstrate the proposed PA architecture is very promising for 60 GHz short-range communication systems.