Pulse swallow frequency divider with idle DFFs automatically powered off

摘要

A pulse swallow frequency divider with ultra-low power consumption is presented. The D flip-flops (DFFs) in the prescaler and the swallow counter are controlled by the modulus control signal and are automatically powered off when they have no contribution to the operation of the divider. Implemented in SMIC 65nm CMOS process, the proposed divider can operate from 0.6 to 4.2 GHz, and the power consumption is 1.35 mW when operating at 2.4 GHz.