Understanding High-Speed Signals, Clocks, and Data Capture

摘要

Ultra high-speed data conversion offers many challenges to the system designer. This is truly a mixed-signal environment in which all the sub circuits have to be considered carefully to allow the ADC to deliver the optimum dynamic performance. Clock systems that meet the low jitter requirements can be realized economically using off-the-shelf components. Similarly, FPGAs are available today with many supporting features for systems that include full LVDS support and clock management circuits.