SystemVerilog goes to next level

摘要

IEEE Standard 1800-2005 SystemVerilog is the industry's first unified hardware description and verification language. A major extension of the established IEEE Std 1364-2001 Verilog language, it brings significant productivity benefits to designersdeveloping complex, high gate-count ASICs, SoCs, ASSPs, and FPGAs. Its advanced design constructs yield more compact RTL code, with typically a two-to-five times reduction in lines of RTL. Its powerful verification constructs help improve productivity with advanced verification techniques and methods.