Metal pitch effects in deep submicron IC design

摘要

Today's silicon designers cannot properly assess the comparative benefits of a particular deep submicron IC fabrication process on the basis of effective gate length alone. The geometry of metal interconnect is now the critical factor in determining technical merits. The rules for judging a IC process have changed as wafer fabrication technology has advanced to allow sub-0.5pm design geometries. Interconnect capacitance now dominates gate delay to the extent that the sole use of an arbitrary minimum effective gate length (L_(eff)) as a figure of process merit can be misleading. A better way to relate technology generations to their metal pitch: see table 1. To see why this shift in thinking has become necessary, let us start with circuit density.