Verification comes into play in Chess/Checkers flow

摘要

London - Target Compiler Technologies NV (Leuven, Belgium) is adding verification capabilities to its Chess/Checkers retar-getable tool flow for intellectual-property design. Since its spin-off in 1996 from Belgian microelectronics research center IMEC, Target Compiler Technologies has supplied retargetable EDA tools for designing, instantiating and programming IP cores. The Chess/Checkers tool suite, in which all the tools are named after famous games, provides an optimizing C compiler, an assembler/disassembler, a linker, an instruction-set simulator (ISS) with source-level debugging capabilities and a hardware description language (HDL) generator. All of the tools are retargetable, based on the processor description language nML.