Intel. Tl discuss strained-engineering tec Tip strain methods used to turbo-charge 90-nm silicon; many firms to follow at IEDM

摘要

Austin, Texas ― Intel Corp. and Texas Instruments Inc. process engineers are opening up about how they have strained ― literally ― to boost the performance of 90-nanometer silicon at only a marginal increase in process cost. Both companies have adopted strained-silicon techniques for the 90-nm node and now have some experience with the approaches. Since disclosing a year ago that it would use strained silicon for its 90-nm silicon, Intel has been quiet about how it created the strain, which stretches the silicon crystal lattice by 1 percent or so, inducing higher mobility in the carriers moving through the channel. The 90-nm process is ramping now for production of Pentium and Celeron processors. Mark Bohr, a senior fellow in charge of process development at the company's Hillsboro, Ore., laboratory, said recently that Intel used different strain-engineering techniques for the PMOS and NMOS transistors on its 90-nm silicon.