SoC testing becomes a challenge

摘要

From the beginning, test has been the poor stepchild of integrated circuit design, ranking somewhere below verification in status, attention and resources. In many organizations test is considered not a design function but rather a part of the manufacturing startup process. Still, just as increasing system-on-chip complexity has elevated verification to an importance rivaling design, fears, near-misses and dire warnings suggest that test is about to take its place as a vital, must-fund design issue that managers will underfund at their imminent peril. As with verification, sheer complexity is part of the driving force behind this new urgency for SoC test. Conventional functional-test techniques―sufficient, say, for an IC of a few thousand gates, or a highly regular IC of a few hundred thousand gates―simply crash and burn on a multimillion-gate SoC comprising a variety of different kinds of cores. Gate count is an issue. But the variety of functional modes, failure modes and test approaches has become an issue as well.