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Cadence aims diagnostics suite at yield engineers

机译:Cadence将诊断套件面向成品率工程师

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摘要

Santa Cruz, Calif. — Bringing its tools to a new group of users, Cadence Design Systems Inc. has introduced Encounter Diagnostics, a set of yield diagnostics tools for IC process and yield engineers. The offering speeds yield ramp-up time for nanometer-scale IC designs, Cadence said. Although design and test engineers may use of the tool's diagnostics features in the initial phases of silicon debug, Encounter Diagnostics will mainly be used within IC manufacturing groups. It thus opens a new audience for Cadence, which has heretofore focused on IC design tools.
机译:加利福尼亚州圣克鲁斯市— Cadence Design Systems Inc.将其工具带给新的用户群,推出了Encounter Diagnostics,这是一套针对IC工艺和良率工程师的良率诊断工具。 Cadence说,提供的速度加快了纳米级IC设计的加速时间。尽管设计和测试工程师可能会在硅调试的初始阶段使用该工具的诊断功能,但Encounter Diagnostics将主要用于IC制造组。因此,它为Cadence开辟了新的受众,而Cadence迄今为止一直专注于IC设计工具。

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