System-Class CPLDs Zip Along At Flank Speeds Of 110-MHz

摘要

As system designers continually try to cut system chip counts, complex programmable logic devices (CPLDs) move to the forefront. Chip densities have increased, allowing the CPLDs to offer more gates and I/O cells. And recently, developments from various suppliers have started to push CPLD complexities beyond the 10,000 gate and 300 I/O mark. With such resources at their disposal, designers can leverage the programmability to craft flexible system solutions.