Edge Profile Effect of Tunnel Oxide on Erase Threshold-Voltage Distributions in Flash Memory Cells

摘要

The erase threshold-voltage $(V_{T})$ distribution in Flash electrically erasable programmable read-only memory cells was investigated versus the tunnel oxide edge profiles in self-aligned shallow trench isolation (SA-STI) and self-aligned poly (SAP) cells. The capacitive coupling with offset voltage correction is transcribed into $V_{T}$ transient for simulating erase $V_{T}$ dispersion without numerous full structure device simulations. It is shown that SAP gives rise to smaller $V_{T}$ dispersion, compared with SA-STI. The $V_{T}$ dispersion resulting from variations in dielectric thickness and oxide edge profiles is shown to fall far short of observed $V_{T}$ distribution, calling for examination of additional process and cell parameters.