Sub-400$^{circ}{rm C}~{rm Si}_{2}{rm H}_{6}$ Passivation, ${rm HfO}_{2}$ Gate Dielectric, and Single TaN Metal Gate: A Common Gate Stack Technology for ${rm In}_{0.7}{rm Ga}_{0.3}{rm As}$ and ${rm Ge}_{1-x}{rm Sn}_{x}$ CMOS

摘要

We report a novel common gate-stack solution for ${rm In}_{0.7}{rm Ga}_{0.3}{rm As}$ n-channel metal-oxide-semiconductor field-effect transistors (nMOSFETs) and ${rm Ge}_{0.97}{rm Sn}_{0.03}$ p-channel metal-oxide-semiconductor field-effect transistors (pMOSFETs), featuring sub-400 $^{circ}{rm C}~{rm Si}_{2}{rm H}_{6}$ passivation, sub-1.75-nm capacitance equivalent thickness (CET), and single TaN metal gate. By incorporating ${rm Si}_{2}{rm H}_{6}$ passivation, an ultrathin ${rm SiO}_{2}$/Si interfacial layer is formed between the high- $k$ gate dielectric and the high mobility InGaAs and GeSn channels. The ${rm In}_{0.7}{rm Ga}_{0.3}{rm As}$ nMOSFET and ${rm Ge}_{0.97}{rm Sn}_{0.03}$ pMOSFET show drive currents of ${sim}{143}$ and ${sim}{rm 69}~mu{rm A}/mu{rm m}$, respectively, at $vert V_{DS}vert$ and $vert V_{GS}-V_{TH}vert$ of 1 V for a gate length $L_{G}$ of 4 $mu{rm m}$. At an inversion carrier density $N_{inv}$ of $10^{13}~{rm cm}^{-2}$, ${rm In}_{0.7}{rm Ga}_{0.3}{rm As}$ nMOSFETs and ${rm Ge}_{0.97}{rm Sn}_{0.03}$ pMOSFETs show electron and hole mobilities of ${sim}{495}$ and ${sim}{rm 230}~{rm cm}^{2}/{rm V}cdot{rm s}$, respectively. At $N_{inv}$ of $4times 10^{12}~{rm cm}^{-2}$, electron and hole mobility values of ${sim}{705}$ and ${sim}{rm 346}~{rm cm}^{2}/{rm V}cdot{rm s}$ are achieved. Symmetric $V_{TH}$ is realized by choosing a metal gate with midgap work function, and CET of less than 1.75 nm is demonstrated with a gate-leakage current density $(J_{G})$ of less than $10^{-4}~{rm A}/{rm cm}^{2}$ at a gate bias of $V_{TH}pm 1~{rm V}$. Using this gate-stack, a ${rm Ge}_{0.95}{rm Sn}_{0.05}$ pMOSFET with the shortest $L_{G}$ of 200 nm is also realized. Drive current of ${sim}{rm 680}~mu{rm A}/mu{rm m}$ is achieved at $V_{DS}$ of