Device-Circuit Analysis of Double-Gate MOSFETs and Schottky-Barrier FETs: A Comparison Study for Sub-10-nm Technologies

摘要

In this paper, we explore the design space of two possible candidate FETs for sub-10-nm technologies—FinFET like double gate MOSFETs (DGFETs) and Schottky-barrier (SB) devices. Though SB devices are expected to have lower ON current, their lower source/drain resistance () can be important in scaled technologies. We evaluate the suitability of the optimized devices for logic and memory designs in the sub-10-nm technologies using a comparative device-circuit analysis based on nonequilibrium Green’s function-based transport models and HSPICE circuit simulation. The devices are optimized with gate-to-source ()/drain () underlap, and proper body thickness to suppress direct source-to-drain tunneling (DSDT). Our analysis shows that introduction of gate-to- underlap provides the benefit of reducing DSDT, while reduced body thickness provides a tradeoff between low DSDT and high . Results also show that DGFETs provide higher drive strength even with larger . As a result, DGFET-based logic shows higher performance, and better read stability for memory while SBFET-based memory shows higher write stability.