A Low-Power HKMG CMOS Platform Compatible With Dram Node 2× and Beyond

摘要

In this paper, a low-cost and low-leakage gate-first high- (k) metal-gate CMOS integration compatible with the high thermal budget used in a 2× node dynamic random access memory process flow is reported. The metal inserted polysilicon stack is based on HfO₂ coupled with Al₂O₃ capping for pMOS devices, and with a TiN/Mg/TiN stack together with As ion implantation for nMOS. It is demonstrated that n and pMOS performance of 400 and 200 (mu ) A/ (mu ) m can be obtained for an OFF-state current of (10^{-10}) A/ (mu ) m, while maintaining gate and junction leakages compatible with low-power applications. Reliability and matching properties are aligned with logic gate-stacks, and the proposed solution is outperforming the La-cap-based solutions in terms of thermal stability.