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Effects of Localized Body Doping on Switching Characteristics of Tunnel FET Inverters With Vertical Structures

机译:局部掺杂对垂直结构隧道FET逆变器开关特性的影响

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摘要

In order to verify the effects of localized body doping (LBD) on alternating current switching performances of tunnel FETs (TFETs) with vertical structures, The TFET inverter composed of n-/p-type TFET with the localized p++ body doping is simulated with the help of mixed-mode device and circuit simulations. As a result, falling/rising delay is significantly improved due to the locally high channel-to-drain side energy barrier induced by the LBD. Furthermore, LBD conditions, such as doping concentration, depth, and width, are optimized to maximize the improvement of falling/rising delay. Based on the optimization results, it is found that enough wide doping width and deep depth are inevitable to minimize the drain voltage (VD)-induced lowering of the locally increased barrier and the increase of ambipolar current and too wide doping width cannot be applied due to the ON-current reduction caused by the degraded controllability of gate voltage on channel similarly to short channel effects. Moreover, the doping width and depth should be adjusted according to LBD concentration.
机译:为了验证局部体掺杂(LBD)对具有垂直结构的隧道FET(TFET)的交流开关性能的影响,模拟了由n- / p型TFET和局部p + / n +体掺杂组成的TFET逆变器借助混合模式器件和电路仿真。结果,由于LBD引起的局部较高的沟道-漏极侧能量势垒,下降/上升延迟得到显着改善。此外,LBD条件(例如掺杂浓度,深度和宽度)已得到优化,以最大程度地降低下降/上升延迟。根据优化结果,发现足够宽的掺杂宽度和深深度是不可避免的,以最小化由漏极电压(VD)引起的局部增加的势垒降低,并且双极性电流的增加和太宽的掺杂宽度均无法应用类似于短沟道效应,由于栅极电压在沟道上的可控制性降低而导致的导通电流降低。此外,应根据LBD浓度调整掺杂宽度和深度。

著录项

  • 来源
    《Electron Devices, IEEE Transactions on》 |2017年第4期|1799-1805|共7页
  • 作者单位

    Department of Electrical Engineering and Computer Science, Inter-University Semiconductor Research Center, Seoul National University, Seoul, South Korea;

    Department of Electrical Engineering and Computer Science, Inter-University Semiconductor Research Center, Seoul National University, Seoul, South Korea;

    Department of Electrical Engineering and Computer Science, Inter-University Semiconductor Research Center, Seoul National University, Seoul, South Korea;

    Department of Electrical Engineering and Computer Science, Inter-University Semiconductor Research Center, Seoul National University, Seoul, South Korea;

    Department of Electrical Engineering and Computer Science, Inter-University Semiconductor Research Center, Seoul National University, Seoul, South Korea;

    Department of Electrical Engineering and Computer Science, Inter-University Semiconductor Research Center, Seoul National University, Seoul, South Korea;

    Department of Electrical Engineering and Computer Science, Inter-University Semiconductor Research Center, Seoul National University, Seoul, South Korea;

    Department of Electrical Engineering and Computer Science, Inter-University Semiconductor Research Center, Seoul National University, Seoul, South Korea;

    Department of Electrical Engineering and Computer Science, Inter-University Semiconductor Research Center, Seoul National University, Seoul, South Korea;

  • 收录信息 美国《科学引文索引》(SCI);美国《工程索引》(EI);
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

    TFETs; Silicon; Doping; Tunneling; Inverters; Logic gates; Delays;

    机译:TFET;硅;掺杂;隧道;逆变器;逻辑门;延迟;
  • 入库时间 2022-08-17 13:13:25

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