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首页> 外文期刊>IEEE Electron Device Letters >Numerical Study of p-n-Doped Poly-Silicon Shield Gate Trench MOSFET With Reduced Output Capacitance
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Numerical Study of p-n-Doped Poly-Silicon Shield Gate Trench MOSFET With Reduced Output Capacitance

机译:输出电容减小的p-n掺杂多晶硅屏蔽栅沟道MOSFET的数值研究

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摘要

This letter proposes a new shield gate (SG) trench MOSFET structure, which utilizes a p-n-doped polysilicon refill as the SG electrode to minimize the total output capacitance or charge. TCAD simulation is carried out to compare the proposed and conventional device structures. It is shown that the proposed structure offers 30% lower Q and 18.2% reduction of inductive switching loss while retaining other attractive characteristics of the SG trench MOSFET.
机译:这封信提出了一种新的屏蔽栅(SG)沟槽MOSFET结构,该结构利用p-n掺杂的多晶硅再填充材料作为SG电极,以最大程度地减少总输出电容或电荷。进行了TCAD仿真,以比较建议的和传统的设备结构。结果表明,所提出的结构在保持SG沟槽MOSFET其他吸引人的特性的同时,降低了30%的Q值并降低了18.2%的电感性开关损耗。

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