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机译:输出电容减小的p-n掺杂多晶硅屏蔽栅沟道MOSFET的数值研究
Electrical and Computer Engineering Department, Illinois Institute of Technology, Chicago, IL, USA;
Electrical and Computer Engineering Department, Illinois Institute of Technology, Chicago, IL, USA;
Electrical and Computer Engineering Department, Illinois Institute of Technology, Chicago, IL, USA;
Logic gates; MOSFET; Capacitance; Electrodes; Quality of service; Switching loss; Leakage currents;
机译:具有屏蔽鳍状栅极的SiC沟槽MOSFET,可减少氧化场和开关损耗
机译:建模沟槽深度对功率MOSFET的栅极-漏极电容的影响
机译:4H-SiC沟槽栅极MOSFET中沟槽底部屏蔽区的自对准形成
机译:过程控制技术可显着减少沟槽沟道型MOSFET的磷掺杂多晶硅中的空隙
机译:在存在栅极隧道效应的情况下,硅MOSFET的电容电压特性。
机译:具有多个外延层的150–200 V分离栅沟道功率MOSFET
机译:模拟沟槽深度对功率MOSFET中栅极-漏极电容的影响
机译:具有高迁移率的常闭4H-siC沟槽栅极mOsFET(预印刷)