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Exploring the Limits of Cobalt Liner Thickness in Advanced Copper Interconnects

机译:探索高级铜互连中钴衬里厚度的极限

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We investigate the performance and reliability characteristics of Cu interconnects with Ta-based barrier layers and Co wetting layers at 7nm node dimensions with a focus on the impacts of reducing the Co thickness from 30 & x00C5; down to 10 & x00C5;. We demonstrate that while reducing Co liner thickness significantly reduces RC delay, there is a significant reduction in electromigration reliability below a thickness of 20 & x00C5; if used in conjunction with a PVD (physical vapor deposition) TaN barrier. However, if the PVD treatment is followed by deposition of a thin ALD (atomic layer deposition) TaN, the Co layer thickness can be scaled down to 10 & x00C5; without any penalty in either electromigration or time dependent dielectric breakdown (TDDB.) The combined PVD/ALD process with 10 & x00C5; Co enables a 14 & x0025; reduction in RC delay relative to our control split.
机译:我们研究了在7nm节点尺寸上具有Ta基势垒层和Co湿润层的Cu互连的性能和可靠性特征,重点关注将Co厚度从30&x00C5减小的影响。降至10&x00C5;。我们证明,虽然减小Co衬里的厚度可以显着降低RC延迟,但在20&x00C5的厚度以下,电迁移可靠性会显着降低。如果与PVD(物理气相沉积)TaN阻挡层配合使用。但是,如果在PVD处理之后沉积薄的ALD(原子层沉积)TaN,则Co层的厚度可以缩小至10&x00C5; PVD / ALD工艺与10&x00C5;结合使用,不会对电迁移或与时间有关的介电击穿(TDDB)造成任何损失。 Co启用14&x0025;相对于我们的控制分割,减少了RC延迟。

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