Analysis of Jitter-Induced Voltage Noise in Clock Channels

摘要

Effects of transmit jitter on lossy clock channel are analyzed analytically by treating the 1010 input clock signal as a sinusoidal wave with a phase modulation that represents jitter. Jitter-to-amplitude-modulation transfer functions are derived for sinusoidal jitter, duty-cycle distortion (DCD), and random jitter (RJ) in terms of the signal transfer function or S-parameters. Input jitter is shown to induce amplitude modulation in the output signal as a result of channel dispersion, leading to voltage noise at the channel output. DCD- and RJ-induced voltage noises are found to scale uniquely with channel loss. To verify the theory, numerical simulations are performed on channels with different losses and at various data rates. The input clock signal is represented with a square wave, and the output signal is calculated by linear superposition of the channel step response. Theoretical and simulation results are found to be in excellent agreement.