Simple FIFO provides data-width conversion

摘要

Many designs require FIFO elastic buffers to form a bridge between subsystems with different clock rates and access requirements. However, in some applications, you need FIFO buffers for data conversion. One example is- the case in which you need to connect an 8-bit ADC to a 16-bit data-bus microprocessor through a FIFO buffer (Figure 1). Unfortunately, most currently available FIFO buffers are unsuitable for this application. This Design Idea describes how to implement a common clock (synchronous version) for an FPGA-based FIFO for data-width conversion with different-width read and write data ports. You can implement this FIFO using a Xilinx (www.xilinx.com) Spartan II Series FPGA.