Co-verification speeds SOC design

摘要

As designs become more complex, standard co-verification techniques are running out of steam. At the same time, many complex SOC (system-on-chip) designs are still using nothing more than a full-functional simulation model of a microprocessor and waveforms to debug complex hardware and software. A full-functional model of a microprocessor fetching and executing code in a logic simulator is not co-verification if the only means of debugging software are waveforms and assembly-language traces. You can realize the difficulty of the problem by looking at the vast array of alternatives available to verify both hardware and software before first silicon is available.