Power-savvy tool replaces clock-tree synthesis

摘要

EDA start-up Azuro Inc wants to help ASIC de-signers get a better handle on IC power conservation and ultimately lengthen the runtimes of their wireless applications. Toward that end, the company recently introduced the PowerCentric EDA tool, a power-savvy replacement for clock-tree synthesis that the company claims yields 10 to 20% power savings.