Designing dual-modulus dividers in an FPGA

摘要

It is often necessary for designers to implement a digital clock divider where the output frequency is not an integer factor of the reference clock. Today's newer FPGA technologies usually contain digital or analog PLLs for frequency synthesis. But because of their specifications, these components are usually applicable only for high clock rates. There is still a need for relatively low-speed clock generation—to connect to peripheral devices, for example.