With the appearance of higher speeds and more DSP macrocells in low-cost FPGAs, more and more design teams are seeing the configurable chips not as glue but as a way to accelerate the inner loops of numerical algorithms, either in conjunction with or in place of the traditional DSP chip. There's a problem, however. You code for a DSP chip in C, and you implement it using a conventional software tool chain with familiar software debugging tools. You configure an FPGA starting in Verilog or VHDL (very-high-speed-integrated-circuit-hardware-description language)-superficially similar to C but in practice profoundly different-and you implement it using a hardware design flow. The two approaches require different skills.
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