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An undergraduate computer engineering rapid systems prototyping design laboratory

机译:本科计算机工程快速系统原型设计实验室

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This paper describes a new two-quarter undergraduate capstone design class in our computer engineering curriculum. Design groups comprised of students from several different areas of specialization (e.g., software systems, very large scale integration (VLSI) devices and circuits, and computer architecture) design, simulate, implement, and evaluate a complete computing system. Typical examples of projects in the current sequence include a pipelined 32-bit RISC processor, a four-cell systolic array processor, and a video game. The goal is to produce simulation and hardware/software codesign as early as possible in the design process. Students execute software on simulation models prior to any hardware implementation. An assembler and a compiler are developed for the new design. Throughout the sequence, students participate in design reviews and must provide documentation of their designs. The final designs are implemented using an array of field programmable gate arrays (FPGAs) contained in a device called a hardware emulator. This allows for ease of design modifications while still having actual hardware for experimentation.
机译:本文介绍了我们计算机工程课程中一门新的为期四分之二的本科教学设计课程。设计小组由来自不同专业领域的学生组成(例如,软件系统,超大规模集成电路(VLSI)的设备和电路以及计算机体系结构),以设计,模拟,实现和评估完整的计算系统。当前序列中项目的典型示例包括流水线32位RISC处理器,四单元脉动阵列处理器和视频游戏。目标是在设计过程中尽早产生仿真和硬件/软件代码。学生在实施任何硬件之前都必须在仿真模型上执行软件。为新设计开发了汇编器和编译器。在整个序列中,学生必须参加设计评审,并且必须提供其设计的文档。最终设计是使用称为硬件仿真器的设备中包含的现场可编程门阵列(FPGA)阵列实现的。这样可以简化设计修改,同时仍具有用于实验的实际硬件。

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