Efficient system level verification and performance analysis using SystemC

摘要

These days, functional verification and performance evaluation of multi-million gate SoCs is a daunting task. There are two major elements that contribute to reduction in efficiency in the overall development process of an SoC: traditional analysis based on spreadsheets and paper calculations are often not accurate enough, especially when the software content is high; and large amounts of hardware dependent software need to be verified against real hardware latencies—a very time-consuming task.