Resource Utilization Optimization with Design Alternatives in FPGA based Arithmetic Logic Unit Architectures

摘要

Designing Arithmetic Logic Unit (ALU) is a combinational logic problem. As ALU has a regular pattern, it can be broken into identical stages connected into cascade through carry chain. We have designed one stage of ALU and then duplicated it depending upon the size required. The design has been tested for 4, 8, 16, 32 and 64- bit width. The idea is resource sharing and functionality sharing technique to design an ALU that leads to a significant saving of resources. Different functionality has been obtained by using a single resource (parallel adder) with different inputs at different times through control circuit. The design through this approach leads to a significant reduction in hardware requirement. The design is implemented in 3s700anfgg484-4 FPGA. Significant reduction in hardware has been achieved. The hardware used has been compared with normal function by function design. Resources saving of 66% have been observed for 4-bit wide ALU implementation on FPGA. For 8 and 16-bit implementation the saving obtained is 65%. A hardware saving of 60% has been obtained for 32 and 64-bit implementation.