Low Power CMOS Design Technique for Power Switches Gating.

摘要

ABSTRACT Power-gating is a low-power design technique to reduce leakage power. It has gained popularity in sub-100-nm CMOS designs, where leakage power is a major contributor to the overall power consumption. It utilizes power switches to power-down the logic blocks during the idle mode to reduce leakage power consumption. Power switches are used as a part of the power-gating technique to reduce the leakage power of a design. To the best of our knowledge, this is the first report in open litera.