A digital circuit Optimization is needed to attain higher performance include terms like minimizing the area occupancy and increasing the speed of operation. In any digital circuit the critical path (longest path delay) decides the operating frequency of the system. The operating frequency of digital circuits can be increased by several techniques such as pipelining and wave-pipelining. The proposed technique is evaluated by implementing 4x4 array multiplier, 4-tap FIR filter using array multiplier and 4-tap DA based FIR filter by using three different schemes: non-pipelining, pipelining and wave-pipelining on Spartan 3E FPGA. The WP array multiplier and FIR filters are operating at higher frequency than by using conventional pipelining and non-pipelining techniques.
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机译：为了获得更高的性能，需要进行数字电路优化，其中包括诸如最小化面积占用和提高操作速度之类的术语。在任何数字电路中，关键路径（最长路径延迟）决定了系统的工作频率。数字电路的工作频率可以通过多种技术（例如流水线技术和波流水线技术）来提高。通过在Spartan 3E FPGA上使用非流水线，流水线和波流水线这三种不同的方案来实现4x4阵列乘法器，使用阵列乘法器的4抽头FIR滤波器和基于4抽头DA的FIR滤波器，以评估所提出的技术。与使用常规流水线和非流水线技术相比，WP阵列乘法器和FIR滤波器的工作频率更高。
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