The main goal of this paper is to provide new low power solutions for very large scale integration. Designers especially focus on the reduction of the power dissipation which shows increasing growth with the scaling down of the technologies. In this paper various technologies at the different levels of the design process have been implemented to reduce the power dissipation at the circuit, architecture and system levels. Previous technologies are summarized and compared with our new approach is presented in this paper. The main objective of this project is the reduction of power dissipation by eliminating the PMOS tree and also by utilizing energy stored at the output can be retrieved by the reversing the current source direction discharging process instead of dissipation in NMOS network with SDCVSL, ADIABATIC LOGIC. It also increases the performance of circuits. Here for this project, I am using MICRO WINDOW TOOL. By using this tool we can develop schematic for all above techniques and also find out the power dissipation.
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