Modified Covalent Redundant Binary Booth Encoding For Fast 64*64 Multiplier Design

摘要

In this paper introducing a novel technique so called redundant binary booth algorithm.The redundant binary in design of high speed digital multiplier is beneficial due to high modularity and carry free addition. Generally,in high radix modified booth encoding algorithm the partial products are reduced in multiplication process. But it yields complexity in producing in generation of hard multiples.Therefore booth encoding scheme along with redundant binary scheme solves this problem by using booth encoding,RB partial product generator,RB partial product accumulator,RB to NB converter stage.In this paper implemented in VHDL