FPGA Based Area Efficient Turbo Decoder For Wireless Communication

摘要

To fulfil the extensive need of high data rate transfer in today's wireless communication systems such as WiMAX and 4G LTE (Long Term Evolution), the turbo codes gives an exceptional performance. They have allowed for near Shannon limit information transfer in modern communication systems. As the performance of these codes increases, their decoding complexity is also increases and so the power consump tion. To reduce this complexity without decreasing its BER (Bit Error Rate) performance a novel modification over SOVA (So ft output Viterbi Algorithm) is proposed in this paper. The proposed model is also implemented on FPGA X ilinx Virtex 5 XC5VLX85ff676-2. The simulation results over MATLAB has been shown, indicates a co mparable BER as compared to LOG-MAP with reduced complexity. The synthesis results over Xilinx FPGA shows an improvement of 12% over area utilization as compared to MAX -LOG-MAP implementation. So with red uced area and low BER, a cost effective solution proposed in this paper