Low Complexity Reconfigurable Turbo Decoder for Wireless Communication Systems

摘要

The development of turbo codes has allowed for near-Shannon limit information transfer in modern communication systems. Although turbo decoding is viewed as superior to alternate decoding techniques, the circuit complexity and power consumption of turbo decoder implementations can often be prohibitive for power-constrained systems. To address these issues, a reduced complexity, low power turbo decoder is proposed, specifically optimized for contemporary FPGA devices. The key power-saving technique in this work is the use of decoder run-time dynamic reconfiguration for different constraint lengths. Max-Log-MAP algorithm, which offers a good compromise between performance and complexity, is selected for implementation. One of the components of this algorithm namely, the branch metric calculation unit is studied and a new design of this unit is proposed. The branch metric normalization scheme proposed here builds upon a sliding window approach and is capable of providing high speed. The implementation of SISO-based turbo decoder with three different constraint lengths (K) on a field programmable gate array (FPGA) achieves a speed of 86.08 % more than the conventional design. The power consumption of the device for various constraint lengths is measured using synopsis design compiler- simplicity premier with DCP 2008 tool. The proposed reconfigurable architecture for a constraint length 'K' consumes very few megawatt of power more than the non-reconfigurable architecture for the corresponding constraint length.