High speed pipelined architecture for cyclic convolution based onFNT

摘要

This paper presents high speed pipelined architecture for cyclic convolution based on Fermat Number Transform (FNT) in the diminished-1 number system. A code conversion method without addition (CCWA) and a butterfly operation method without addition (BOWA) were used to perform the FNT and its inverse (IFNT). The point wise multiplication in the convolution is accomplished by modulo 2n+1 partial product multipliers (MPPM) and output partial products which are inputs to the IFNT. Thus modulo 2n+1 carry propagation additions are avoided in the FNT and the IFNT except their final stages and the modulo 2n+1 multiplier. Buffers were used after each and every block in order to store the results of previous block. Introduction of buffers after each block has enabled the architecture to fetch the inputs and outputs at every clock cycle. Compared with the parallel architecture, the proposed one has better throughput and speed