Virtual metrology on semiconductor manufacturing based on Just-in-time learning * * This work is a part of the European project ”INTEGRATE”, and carried by STMicroelectronics Fab

摘要

This paper deals with missing data in semiconductor manufacturing derived from measurements sampling strategies. The idea is to construct a virtual metrology module to estimate non measured variables using a new modified Just-In-Time Learning approach (JITL). The classical method has been proposed and applied in the chemical process. This latter presents some drawbacks and our main contribution is to improve the existing algorithm version of the JITL approach. The effectiveness of our proposed method is illustrated by using simulation examples that enable to compare simulation results obtained with the old and the new version.