Time/frequency-limited positive-real truncated balanced realizations

摘要

Many integrated electrical circuits and networks comprise of large RLC ladders. These complex circuits are described by high-order positive-real transfer functions. To simplify the design and analysis of these complex systems, model reduction techniques are used. It is of critical importance that the positive-real structure of the transfer function is retained in the reduction process. Moreover, it is often of the interest that the reduced-order surrogate model accurately approximates the original system within a limited time or frequency range. In this paper, truncated balanced realizations which ensure good accuracy in the desired time or frequency range without losing the positive-real structure of the original system are presented. These realizations can even be computed for non-minimal systems. Easily computable a priori error bound expressions are also derived for the proposed algorithms. The algorithms are tested on benchmark examples and comparison with the existing techniques is shown to highlight the efficacy of the proposed algorithms.