The digital processing signal is one of the subdivisions of the analog digital converter interface; data transfer rate in modern telecommunications is a critical parameter. The greatest feature of parallel conversion rate (4-bit parallel Flash 5/s converter) is designed and modeled in 0.18 micron CMOS technology. Low speed swing operation as analog and digital circuits leads to high speed of low power operation power with 70 mVt 1.8 V A/D converter from the power dissipated during operation in the 5 GHz range. Average offset is used to minimize the effect of the bias of a comparator. This paper contains the 8-bit encoder of the metrical term code to direct binary code decreasing power consumption, which is shown by results and comparison with other designs using computer simulation. The results of the flash ADC time-interleaved are a more significant improvement in terms of power and areas than those previously reported.
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机译：数字处理信号是模拟数字转换器接口的细分之一。现代电信中的数据传输速率是一个关键参数。并行转换速率（4位并行Flash 5 / s转换器）的最大特点是采用0.18微米CMOS技术进行设计和建模。低速摆幅操作（作为模拟和数字电路）可在5 GHz范围内的运行过程中消耗70 mVt 1.8 V A / D转换器，从而实现低功耗运行电源的高速运行。平均偏移量用于最小化比较器偏置的影响。本文包含度量术语代码的8位编码器，以指导二进制代码降低功耗，这通过结果进行了显示，并与使用计算机仿真的其他设计进行了比较。与以前报告的结果相比，时间交错的闪存ADC的结果在功率和面积方面有了更大的改进。
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