A new FinFET flip-flop operating in low source voltages

摘要

A flip-flop is one of the most widely used cells in digital circuits. This paper proposed a new FinFET flip-flop operating in low source voltages. The four flip-flops using different design styles, named as master-slave flip-flop based on transmission gate, brute-force master-slave flip-flop based on transmission gate, brute-force master-slave flip-flop based on clocked CMOS, and the proposed new flip-flop are compared in terms of delay time, power consumption, and power delay product. All circuits are simulated with HSPICE at a PTM (Predictive Technology Model) 32nm FinFET technology. The results show that the proposed flip-flop obtains good performance on delay, power consumption, and power delay product. Especially in low source voltages, the proposed flip-flop achieves great improvement in power delay product, compared with the other ones.