Low-power flip-flops operating in low voltages and their performance variations considering process deviations

摘要

Lowering supply voltage of circuits can achieve large energy dissipation savings. However, as the reduction of the process feature size scaling down to nano dimension, process deviation influence on the circuit functionality and performance is more and more serious. The circuits operating in low voltages suffer from poor performance and increased variations. This paper presents two new low-power FinFET flip-flops with master-salve structure. In the proposed flip-flops, both master and salve latches use dual rail schemes to promote their operating speed and reduce performance variations caused by process deviations. The proposed flip-flops were investigated in terms of delay, energy dissipation, energy delay product, and variations of propagation delay considering process deviations. The results show that the proposed flip-flops achieve large performance improvements and have small performance variations compared with the typical counterparts in wide voltage ranges from 0.6 V to 1.0 V.