Logic Synthesis for a Regular Layout

摘要

New algorithms for generating a regular two-dimensional layout representation formulti-output, incompletely specified Boolean functions, called, Pseudo-Symmetric BinaryDecision Diagrams (PSBDDs), are presented. The regular structure of the functionrepresentation allows accurate prediction of post-layout areas and delays before thelayout is physically generated. It simplifies power estimation on the gate level and allowsfor more accurate power optimization. The theoretical background of the new diagrams,which are based on ideas from contact networks, and the form of decision diagramsfor symmetric functions is discussed. PSBDDs are especially well suited for deepsub-micron technologies where the delay of interconnections limits the device performance.Our experimental results are very good and show that symmetrization of reallifebenchmark functions can be done efficiently.