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A Class of High-Rate Low-Complexity Error-Detecting RLL Codes

机译:一类高速率,低复杂度的检错RLL代码

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We present a new methodology for the construction of high-rate channel modulation run-length-limited RLL codes. Simple modulation encoders and decoders are constructed, with low error propagation during decoding. They combine partial error detection capability (PED) to boost the performance of a concatenated outer Error Correction Code (ECC) [1]. Moreover, current systems are using low redundancy ECC, and the overall rate is mainly determined by the inner modulation code rate, which critically is to be maintained high. Code rates , for example, 16/17, 24/25 and higher are achievable, with efficiency exceeding 0.94 and 0.96, respectively. The proposed fixed length block decodable codes, are generalized schemes of the type for .
机译:我们提出了一种用于构建高速率信道调制行程限制RLL码的新方法。构建了简单的调制编码器和解码器,在解码过程中错误传播率低。它们结合了部分错误检测功能(PED),以增强级联外部错误校正码(ECC)[1]的性能。而且,当前系统使用低冗余ECC,并且总速率主要由内部调制码率确定,内部调制码率必须保持较高。可以达到16 / 17、24 / 25和更高的编码率,效率分别超过0.94和0.96。提议的固定长度块可解码代码是的类型的通用方案。

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