UVM Based Reusable Verification IP for Wishbone Compliant SPI Master Core

摘要

The System on Chip design industry relies heavily on functional verification to ensure that the designs arebug-free. As design engineers are coming up with increasingly dense chips with much functionality, thefunctional verification field has advanced to provide modern verification techniques. In this paper, wepresent verification of a wishbone compliant Serial Peripheral Interface (SPI) Master core using a SystemVerilog based standard verification methodology, the Universal Verification Methodology (UVM). Thereason for using UVM factory pattern with parameterized classes is to develop a robust and reusableverification IP. SPI is a full duplex communication protocol used to interface components most likely inembedded systems. We have verified an SPI Master IP core design that is wishbone compliant andcompatible with SPI protocol and bus and furnished the results of our verification. We have usedQuestaSim for simulation and analysis of waveforms, Integrated Metrics Center, Cadence for coverageanalysis. We also propose interesting future directions for this work in developing reliable systems.