Survey on Power Optimization Techniques for Low PowerVLSI Circuitsin Deep Submicron Technology

摘要

CMOS technology is the key element in the development of VLSI systems since it consumes less power.Power optimization has become an overridden concern in deep submicron CMOS technologies. Due toshrink in the size of device, reduction in power consumption and over all power management on the chipare the key challenges. For many designs power optimization is important in order to reduce package costand to extend battery life. In power optimization leakage also plays a very important role because it hassignificant fraction in the total power dissipation of VLSI circuits. This paper aims to elaborate thedevelopments and advancements in the area of power optimization of CMOS circuits in deep submicronregion. This survey will be useful for the designer for selecting a suitable technique depending upon therequirement.