首页> 外文期刊>International Journal of Network Security & Its Applications >Predominance of Blowfish Over Triple Data Encryption Standard Symmetric Key Algorithm for Secure Integrated Circuits Using Verilog HDL
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Predominance of Blowfish Over Triple Data Encryption Standard Symmetric Key Algorithm for Secure Integrated Circuits Using Verilog HDL

机译:使用Verilog HDL在安全集成电路中三重数据加密标准对称密钥算法中的河豚优势

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Computer data communication is the order of the day with Information Communication Technology (ICT)playing major role in everyone’s life, communicating with smart phones, tabs, laptops and desktops usinginternet. Security of the data transferred over the computer networks is most important as for as anorganization is concerned. Hackers attempt hard to crack the software key and indulge in cyber crimes. Inthis paper, the main concern is not only to provide security to the data transferred at the software level butit provides the security at hardware level by the modified Blowfish Encryption and Decryption Algorithms.It results minimum delay, high speed, high throughput] and effective memory utilization compared toBlowfish (BF) and Triple Data Encryption Standard (TDES) algorithms. The implementation of Blowfishwith modulo adder and Wave Dynamic Differential Logic (WDDL) is to provide security againstDifferential power analysis (DPA). In the proposed four implementations, BF with constant delay n-bitadder (BFCDNBA) yielded minimum delay, maximum frequency, high memory utilization and highthroughput compared to BF with modulo adder and WDDL logic (BFMAWDDL), BF with modulo adder(BFMA) and TDES algorithms. The VLSI implementation of Blowfish and TDES algorithms is done usingVerilog HDL.
机译:计算机数据通信已成为日常工作,信息通信技术(ICT)在每个人的生活中发挥着重要作用,并通过互联网与智能手机,标签,笔记本电脑和台式机进行通信。就组织而言,通过计算机网络传输的数据的安全性是最重要的。黑客努力破解软件密钥,沉迷于网络犯罪。本文的主要关注点不仅在于为软件级传输的数据提供安全性,还在于通过改进的Blowfish加密和解密算法在硬件级提供安全性,从而实现最小的延迟,高速,高吞吐量]和有效的内存。与河豚(BF)和三重数据加密标准(TDES)算法相比。带有模加法器和波动态差分逻辑(WDDL)的Blowfish的实现是为了提供针对差分功率分析(DPA)的安全性。在提出的四种实现中,与带模加法器和WDDL逻辑的BF(BFMAWDDL),带模加法器(BFMA)和TDES的BF相比,具有恒定延迟n位加法器(BFCDNBA)的BF具有最小的延迟,最大频率,高内存利用率和高吞吐量。算法。使用Verilog HDL完成了Blowfish和TDES算法的VLSI实现。

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