FPGA Implementation of H.264 CAVLC Decoder Using High-Level Synthesis

摘要

CONTEXT ADAPTIVE VARIABLE LENGTH CODING (CAVLC) is a method designed for coding residual pixel data after transform and quantization, in which different codes with variable length are chosen based on recently coded coefficients. Coded bitstream can be stored or transmitted. This method is optional in widely adopted H.264 video coding standard. The entire algorithm is a complex one, and also difficult to implement efficiently in Field-Programmable Gate Array (FPGA), due to data dependency. When the complexity of the Register Transfer Logic (RTL) implementation rises, it impacts the duration and costs of development. Therefore, usage of High Level Synthesis (HLS) may be beneficial with these types of projects. In this paper first known to authors implementation of CAVLC and Exp-Golomb decoders for H.264 intra decoder in Impulse C language will be presented and compared with other implementations. Proposed solution is able to decode more then 720p@40fps with FPGA module clock at 166MHz.