Design of a New Power Efficient Explicit-Pulsed Dual Edge Triggered Sense-Amplifier Flip-Flop

摘要

In this paper a new dualedge triggered senseamplifier flipflop (NEWDETSAFF) is proposed. The proposed flipflop presets its storage nodes to a medium voltage level between VDD and VSS just before input capturing. By embedding dualedge triggering mechanism