Design and simulation of 64 point FFT using Radix 4 algorithm for FPGA Implementation

摘要

The Fast Fourier Transform (FFT) is one of the rudimentary operation s in field of digital signal, image processing and FFT processor is a critical block in all multi carrier systems used primarily in the mobile environment. Fast Fourier transform (FFT) is an efficient implementation of the discrete Fourier transform (DFT). The portability requirement of these systems is m ainly responsible for the need of low power FFT architectures. . In this study, the development of 64 point FFT, based on Decimation In Time (DIT) domain using Radix 4 algorithm. The complex multiplier is one of the most power consuming blocks in the F FT processor. A significant property of the proposed method is that the critical path of the address generator is independent from the FFT transform length N, making it extremely efficient for large FFT transforms. The results confirm the speed and area ad vantages for large FFTs. Although only radix 4 FFT address generation is presented in the paper, it can be used for higher radix FFT.