PERFORMANCE ENHANCED ROUTER DESIGN FOR NETWORK ON CHIP

摘要

Network on chip is a new paradigm for on chip design that is able to sustain the communication provisions for the SoC with the desired performance. NOC applies networking methodology concepts to system on chip data transfer and it gives noticeable elevation over conventional bus based communication. NOC router is the backbone of on chip communication which directs the flow of data. In NOC router the arbiter is used during number of inputs request for the similar out port. Arbiter generates the grant based on the priority and previous granted input. For NOC router we have design the efficient round robin arbiter and analyse the power and area. In this paper on chip router is designed with a buffering technique of FWFT based asynchronous FIFO which improves timing and reduce power consumption. The proposed design of router is simulated and synthesized in Xilinx ISE 13.2 and the source code is written in Verilog. Cadence soc encounter of technology ami035 is used to generate layout of router and RTL compiler is used to compute area, power and timing.