BIST for SOC Interconnects Using Extended Serial TAM in IEEE 1500 Standard

摘要

In this paper, we proposed BIST-based architecture to at-speed test of crosstalk faults for SOC interconnects. This architecture includes IEEE 1500 wrapper enhanced cells intended for Mutiple Victim Test (MVT) model test patterns generation and analysis test responses. In order to fully comply with conventional IEEE 1500 standard, one new instruction is used to control cells and test pattern generator controller in serial test access mechanism of the standard.