An Attempt to Improve the Processor Performance by Proper Memory Management for Branch Handling

摘要

The performanceof the processoris highly dependent on the regular supply of correct instruction at theright time. Whenever a data miss is occurring in the cache memory the processor has to spend more cyclesfor the fetching operation. One of the methodsused to reduce instruction cachemiss is the instructionprefetching,which in turn will increase instructions supply to the processor.The technology developments inthese fields indicates that in future the gap between processing speeds of processor and data transferspeed of memory islikely to be increased. Branch Predictor play a critical role in achievingeffectiveperformance in many modernpipelined microprocessor architecture.Prefetching canbe done either with software or hardware. In software prefetching the compiler will insert aprefetch code in the program. In this case as actual memory capacity is not known to the compiler and itwill lead to some harmful prefetches. In hardware prefetching instead of inserting prefetch code it willmake use of extra hardware and which is utilized during the execution. The most significant source of lostperformance when the process waiting for the availability of the next instruction. Thetime that is wasted incase of branch misprediction is equal to the number of stages in the pipeline, starting from fetch stage toexecute stage. All the prefetching methods are givenstress only to the fetching of the instruction for theexecution, not to the overall performance of the processor. The most significant source of lostperformanceis,when the process is waiting for the availability of the next instruction. The time that iswasted in case of branch misprediction is equal to the number of stages in the pipeline, starting from fetchstage to execution stage.This paper we made an attemptto study thebranch handling in a uniprocessingenvironment, whenever branching is identified instead of invoking the branch prediction the proper cachememory management is enabled inside the memory management unit